In typical computer systems, signals generated by a first functional logic block (for example, a memory controller) destined for a second functional logic block (for example, a memory) are transferred via clocked latches or buffers. The buffers are coupled to interconnect comprising routed “traces,” i.e., conductive media such as copper wiring or print within a circuit board. Output signals from the buffers are switched at a given clock rate to propagate the signals, via the interconnect, from the first functional block to the second.
Traces in the interconnect have varying lengths depending upon the points they are connected between. Thus, signal propagation times or “flight times” from the switched buffers vary, corresponding to the length of the trace they must travel in the interconnect. To maintain timing integrity, operations on data transferred over the interconnect must accommodate the longest trace (and correspondingly slowest signal) of the interconnect.
In many systems, the output buffers are clocked off the same clock and consequently switch simultaneously (an effect called “simultaneously switching outputs” (SSO)). However, SSO has effects which tend to degrade system performance. In particular, SSO causes large, rapid current changes which, in view of the known relation V=L(di/dt), generate voltage drops (ringing) across inductances present in the system circuitry. Such voltage drops cause the switched buffers to become power-starved. This causes the buffer delays to increase, or “push out.” The SSO noise on the power lines can also cause other signals on the same power delivery network as the switched buffers to switch in error. If these other signals are clocks, the erroneous switching can generate timing problems in the system.
As noted above, trace lengths in interconnect typically vary. Thus, while with SSO the output buffers switch simultaneously, the output signals in many cases do not arrive at the receiving end of the interconnect simultaneously. This phenomenon is particularly prevalent in the case of narrow-to-wide interfaces; i.e. interfaces wherein a substantial degree of “fan-out,” or widening is exhibited in the interconnect from one interface to another. The fan-out is due to a physical widening in the space the traces occupy, usually as a result of the spacing between the traces increasing to meet the width of the second functional block.
As further noted above, the timing at a receiving end of interconnect is dictated by the slowest signal propagated by the interconnect; i.e., the signal propagated on the longest point-to-point path of the interconnect. Accordingly, a time margin exists, proportional to the difference in flight time between the fastest signal and the slowest signal, during which none of the signals can be used. Instead, the faster signals must wait for the slower signals to “catch up.” The timing push-out caused by SSO only exacerbates the worst case min-max in timing difference.
Thus, techniques have been developed to exploit this time margin to reduce the undesirable effects of SSO. According to such techniques, output buffers are switched in a staggered or phased fashion, as opposed to simultaneously. This has the effect of spreading out the L(di/dt) voltages over a wider time interval, reducing some of the detrimental consequences of SSO.
However, such techniques tend to be inflexible or constrained in their application, because they are not adaptable to the different ranges and patterns of trace lengths that can result from particular board layouts.
A complementary problem associated with varying trace lengths in a board layout involves the sampling of data arriving at a receiver interface, as opposed to data transmitted from an output or driver interface. When a data signal or group of data signals arrive at a receiver interface, there is a period of time known as a “data valid” period during which the signal must be sampled. Ideally, to avoid timing complexity, the “data valid” period for all of the signals of an interface would overlap, so that all of the signals could be sampled at the same time. However, this is typically not possible because of the different arrival times of the signals depending on the trace lengths imposed by a particular board layout. In particular, the “data valid” period of some signals or groups of signals may not overlap with the “data valid” period of any other signals or groups of signals. Thus, multiple sampling clocks must be typically be used to sample signals arriving at a receiver interface, depending upon when their “data valid” period occurs.
Techniques are known for arranging sampling times in accordance with the arrival times of signals. However, as with known methods for handling the effects of SSO, techniques for arranging sampling times are not readily adaptable to the different ranges and patterns of trace lengths that can result from particular board layouts.
In view of the foregoing considerations, a more flexible and adaptable approach, both for ameliorating the effects of SSO at an output or driver interface, and for simplifying data sampling at a receiver interface, is called for.